As memories grow faster, denser and more complex, there is an increased demand for ABIST (Array Built-In Self-Test) structures offering high speed and high test coverage, while at the same time consuming minimal area of a semiconductor chip. By way of example, FIG. 1 shows the block diagram architecture of a state of the art SRAM macro 10 provided with an ABIST unit 11. A similar architecture is described in U. S. Pat. No. 5,173,906 of common assignee. The functional units shown in FIG. 1, either form part of a stand-alone SRAM or the SRAM macro of a logic array of an integrated circuit chip. In the latter case, the chip may include a plurality of such macros, each provided with its own dedicated ABIST unit. The integrated circuit chip described is part of a wafer fabricated in a very large scale integration (VLSI) semiconductor technology and is presumed to be designed according to level-sensitive scan design (LSSD) rules.
As known to those skilled in the art, the SRAM macro 10 shown in FIG. 1 has three basic modes of operation: a SYSTEM mode, in which. the SRAM macro 10 operates normally, i.e., where the memory unit 12 is either read or written, using the data-in signals DATAIN1 to DATAINM, the SRAM address signals ADDIN1 to ADDINP, and the read/write control signal R/WIN (where in M and P are, respectively, the bit widths of the data-in bus DATAIN and the SRAM address bus ADDIN). A second mode is required to satisfy LSSD requirements: the SCAN mode which is used for initializing/analyzing (SCAN-IN/SCAN-OUT) all the data of the latch pairs that form an LSSD chain. Finally, a third mode: the ABIST mode, in which the functionality of memory unit 12 is tested. It is a self-test which is first performed in a manufacturing environment before the chip is commercially released. A slightly different, more relaxed self-test is performed while the chip is incorporated in a system, for example, at the customer location, and thus in a system environment. As a result, the ABIST mode is used in different environments referred to hereinafter as the ABIST manufacturing sub-mode and the ABIST system sub-mode.
In the ABIST mode, according to the fundamentals of the self-test technique, the ABIST unit 11 generates a plurality of test vectors. Each test pattern consists of a set of deterministic 0's and l's that are first written into memory unit 12, then read and compared with an expected pattern. The test pattern sequences play a key role in exercising the memory unit 12 to verify whether the memory unit 12 under best is functioning properly, i.e., to determine whether the READ and WRITE operations were successful. To that end, the ABIST unit 11 generates self-test data signals STDATA, self-test address signals STADD, and the self-test read/write control signal STRW.
Three groups of multiplexers select the signals to be fed to the memory unit 12. These include either the external signals mentioned above which are generated from outside the SRAM macro 10, namely, DATAIN1 . . . DATAINM, ADDIN1 . . . ADDINP, and R/WIN signals, or the internal self-test signals generated by the ABIST unit 11 mentioned above, namely, the STDATA, STADD, and STRW signals. The multiplexers forming these three groups are respectively referenced as 13-1 to 13-M, 13'-1 to 13'-P, and 13". The selection is made by the ABIST signal. Normally, external signals are selected when the ABIST signal is held at a logic "0", whereas signals that are internally generated by the ABIST unit 11 are selected when it is held at a logic "1". The ABIST signal thus allows the SRAM macro 10 to operate either in the SYSTEM mode or in the ABIST mode. The three groups of multiplexers 13-1 to 13-M, 13'-1 to 13'-P, and 13" form multiplexer block 13. The outputs of the first and second groups are labelled DATA bus and ADD bus, with M and P respective bit widths. The output of multiplexer 13" is a single line that carries the R/W control signal that determines the READ/WRITE operating mode of memory 12.
The data-out signals that are outputted by memory 12 are stored in a plurality of data-out L1/L2 pairs of latches (14-1 to 14-M) forming the data-out shift register 14. Generally, these data-out latch pairs are incorporated into memory 12. The data-out signals that are outputted by the L1 and L2 latches are labelled DATAOUT1 to DATAOUTM (DATAOUT bus) and DOUT1 to DOUTM (DOUT bus), respectively.
In the ABIST mode, after performing a READ operation, expected data signals labelled EXDATA are generated by the ABIST unit 11 on the EXDATA bus and are compared in the data compression unit 15 via data-out signals DOUT1 to DOUTM. Typically, only four test patterns are used on each word of the memory unit 12: alternate 0's and l's, i.e., 0101 . . . 01 and 1010 . . . 10, all 0's and all l's. Alternatively, there are only four self-test data signals, labelled STDATA0, STDATA1 and their respective complements. Because of the particular structure of these four test patterns, the data-out signals DOUT1 to DOUTM are divided into even and odd data-out signals. The even data-out signals that are outputted from the data-out shift register unit 14 are labelled DOUT2, DOUT4, . . . , DOUT2j, and likewise, the odd data-out signals are labelled DOUT1, DOUT3, . . . , DOUT(2j- 1), where j is an integer equal to M/2, assuming that M is an even number. Since all the even and odd numbered bits of the data-out signals have simultaneously the same `0` or `1` value, only two expected data signals are required, each one consisting of a single bit, EXDATA0 and EXDATA1. For instance, assuming the data-out signals to be read on the DOUT bus are: 010101 . . . 01, the expected data signal EXDATA0 (for the even numbered bits) will be "1" and the expected data signal EXDATA1 (for the odd numbered bits) "0". EXDATA0 and EXDATA1 signals are thus the expected results for the even and odd data-out signals, respectively. Finally, data compression unit 15 generates a signal labelled RESULT which is held at a high logic level, namely, at "1", if a mismatch occurs during the comparison. By mismatch, it is to be understood that at least one data-out signal does not have the same logic value as its corresponding even or odd expected data generated by the ABIST structure 11. This mismatch is often caused by a defective word line in the memory unit 12 at a predetermined address. This mismatch is usually referred to as a "fail". Alternatively, if all data-out signals match the corresponding even or odd expected data signals (which means no fail is detected), the RESULT signal is held at the low logic level, i.e. at "0". The RESULT signal, which is often referred to as the FAIL FOUND LAST CYCLE signal, indicates after completing a READ operation, whether the memory unit 12 at the current address is defective. The RESULT signal is thus indicative of the fail/no fail status of memory unit 12 on a cycle by cycle basis. Another key component of the state of the art SRAM macro 10 is the fail register unit 16. It is required because, in the ABIST manufacturing sub-mode, the addresses of the defective word lines have to be identified, then memorized for subsequent use in the SYSTEM mode. When the RESULT signal is raised to a logic "1", indicating the presence of a failure, the word portion of the current address generated by the ABIST unit 11 on the STADD bus, labelled STADD*, is stored in a bank of pairs or latches of the fail address register 16. This stored word address thus corresponds to the address of a defective word line.
The ABIST unit 11 also generates a CNOOP (NOOP stands for NO OPERATION) signal to inhibit the ABIST self-test mode when the totality of the test pattern sequences has been fully exercised on memory 12. This signal is required when there is a plurality of SRAM macros embedded in a single semiconductor chip. These macros may have different sizes requiring different durations for their respective test. The CNOOP signal generated by the ABIST unit of each SRAM macro allows the memory units of all macros to be simultaneously tested.
Clocking the SRAM macro 10 is achieved using the standard procedures in accordance with LSSD rules. In state of the art architecture, a SRAM as illustrated in FIG. 1, clocking would normally be implemented by standard external LSSD clock signals labelled A, B, C, S, and CS (CHIP SELECT for a stand-alone SRAM chip or ARRAY SELECT for a SRAM macro). Note that the clock signal S, which is substantially the same as the clock signal B, is applied to the L2 latches of the latch pairs 14-1 to 14-M of the data-out shift register 14. In the ABIST manufacturing sub-mode, the clock and CS signals are derived from the tester. In the ABIST system sub-mode, these signals are derived from the system clock. The SCAN-IN (SI) signal is applied to the ABIST unit 11 according to standard LSSD rules, as illustrated in FIG. 1. However, for sake of simplicity, the SCAN-OUT signal generated by ABIST 11 in response to the SCAN-IN signal to be applied to the next latch pair, etc., along the whole LSSD chain, is not shown. In the following description, only latches will be referred to while it is clear, that according to LSSD rules, they are in reality latch pairs. All these signals are directly applied to ABIST 11 and/or to the memory 12, except for the clock C and CS signals. The clock signal C is applied to one input of a 2-way AND gate 17A. The CS signal is applied to one input of the 2-way AND gate 17B. The CNOOP signal is applied to the second input of AND gates 17A and 17B as a gating signal in order to block, when needed, the transmission of the respective clock C and CS signals. This occurs when the self-test has been completed in the ABIST mode and permanently in the SYSTEM mode. The A, B, and S clock signals are used during the SCAN mode, whereas the B, C, S and CS signals are used during the ABIST mode. The CS signal is used alone in the SYSTEM mode while the LSSD clock signals are held in a non-active state. Numeral 18 schematically illustrates the clock distribution scheme in the SRAM macro 10 and also includes the internal chip clock distribution network servicing it. This terminates the description of a state of the art SRAM macro provided with an ABIST structure. Because the data compression unit 15 performs the comparison between the data-out signals, i.e., between the data read from memory 12 and the expected data signals generated by ABIST 11, the SRAM macro 10 is an essential element to determine the integrity of the READ/WRITE operation. Moreover, as the cycle times of systems using such SRAM macros are reduced, there is a real need to perform this comparison at the highest possible speed. A conventional technique of data compression consists of comparing the data-out signals with the expected data signals, on a bit per bit basis, using exclusive-OR gates and ORing the result. This comparison is generally made using standard library logic books. Together with the four above mentioned test patterns, the data compression circuit 20 shown in FIG. 2, may be viewed as a typical implementation of a conventional data compression circuit to fit the data compression unit 15 of FIG. 1.
Referring now to FIG. 2, a first set of input terminals, labelled 21-1 to 21-2j, are connected to the outputs of the L2 latches of latch pairs 14-1 to 14-M (see FIG. 1), so that the data-out DOUT1 to DOUT2j (DOUTM) are respectively applied thereat. Two additional input terminals, labelled 22-1 and 22-2, forming a second set, are connected to ABIST 11, so that the EXDATA1 and EXDATA0 signals are respectively applied thereon.
The data compression circuit 20 thus consists of a plurality of 2-way XOR logic gates (as many XOR gates as there are data-out signals or bits), labelled 23-1 to 23-2j respectively, and one 2 j-way OR logic gate labelled 24. The first input of each 2-way XOR gate is connected to the corresponding circuit 20 input terminal and data-out signal. For instance, the first input of XOR gate 23-1 is connected to input terminal 21-1 where data-out signal DOUT1 is applied. The second input of each 2-way XOR gate is connected to either EXDATA0 or EXDATA1 signal. EXDATA0 signal is connected to the second input of XOR gates labelled 23-2, 23-4, . . . , 23-2j. Similarly, EXDATA1 signal is connected to the second input of XOR gates labelled 23-1, 23-3, . . . , 23-(2j-1). The 2j inputs to the 2 j-way 0R gate 24 are connected to the 2j outputs of the 2-way XOR gates 23-1 to 23-2j. The RESULT signal is generated by the 2 j-way OR gate 24 and is available at output terminal 25-1. Operation of circuit 20 is relatively simple. Each of the odd data-out signals DOUT1, . . . , DOUT(2j-1) is compared to the signal EXDATA1 and each of the even data-out signals DOUT2, . . . , DOUT2j is compared to the signal EXDATA0 using an XOR tree. If there is a mismatch in at least one XOR gate 23-1 to 23-2j, the corresponding output thereof will be raised to "1", and the RESULT signal generated by 2 j-way OR gate 24 will be raised to "1", thereby indicating the existence of a fail in the READ operation.
Implementing the conventional data compression circuit 20 in the SRAM macro 10 of FIG. 1, whose memory 12 generates, say, 128 data-out signals, using a standard 0.8 micron CMOS technology would require about 1110 devices for a total of 171 logic books. What is important is that the path delay runs through 5 stages. Indeed, the full set of XOR gates 23-1, . . . , 23-2j accounts for one stage, while OR gate 24 accounts for four stages when broken down into elementary logic books, because of the high number of inputs (128). As a result, the total nominal delay of circuit 20 when implemented with the above 0.8 micron technology is about of 4.0 ns.
With the selected four test patterns of each of memory word, all the even numbered bits of any data-out signals are simultaneously at the same `0` or `1` value. This is not very efficient to compare the data-out signals with the expected data signals in terms of circuit density, delay and fan-in. A similar reasoning applies to the odd numbered bits of the data-out signals. Each XOR gate, e.g., 23-1 of circuit 20, is rather complex, because it uses many devices. Moreover, circuit 20 has a large fan-in with respect to the expected data signals. For example, as apparent from FIG. 2, with 128 data-out signals, for each expected data, the fan-in is 64. This fan-in has a strong negative impact on the speed of circuit 20. As a result, circuit 20 is limited to memory units provided with a limited number of data-out signals and should the number thereof increase, it would no longer be operative.